1. Technical Field
The present disclosure relates to a semiconductor memory device and, more particularly, to a method of generating an analog reference voltage, an analog reference voltage generator, an analog-to-digital converter (ADC) including the analog reference voltage generator, and an image sensor including the ADC.
2. Discussion of Related Art
Analog signals, for example, analog signals output from pixels of an image sensor, should be converted into digital codes (or digital signals) to realize the reproduction of an image. Analog-to-digital (AD) conversion is performed using a device for converting an analog signal to a digital signal, that is, an analog-to-digital converter (ADC).
For the AD conversion, it is typically required to compare an input analog signal with a reference voltage signal. Generally, a circuit generating the reference voltage is referred to as an analog reference voltage generator, an example of which is a ramp signal generator. The ramp signal generator is a circuit that outputs a signal periodically rising or falling and having two or more signal waveforms according to the type of input analog signal.
FIG. 1 is a circuit diagram of a conventional analog reference voltage generator in the form of an integrator. The offset signal OFFSET is an input signal that determines an initial value of an output signal OUT, and a gain signal GAIN is an input signal that determines a unit variation of the output signal OUT changing in response to clock signals Clk1 and Clk2. The reset signal Reset controls the switching operation of a switch S5 to discharge a capacitor C2, so that the output signal OUT is maintained at an offset voltage level. The first and second clock signals Clk1 and Clk2 are non-overlapped clock signals, that is, respective high periods thereof do not overlap in time.
FIG. 2 is a graph showing the output signal OUT indicated in FIG. 1. The output signal OUT increases repeatedly when the clock signal Clk1 or Clk2 progresses. The above-described analog reference voltage generator accumulates charges during the period of the clock Clk1 or Clk2 at a ratio of the capacitors, that is, C1/C2, and outputs the output signal OUT according to the result of the accumulation.
FIGS. 3A, 3B, and 3C illustrate the operation of the analog reference voltage generator illustrated in FIG. 1. FIG. 4 shows waveforms of the first and second clock signals Clk1 and Clk2 and the output signal OUT. Referring to FIGS. 3A and 4, when the reset signal Reset is enabled, the output signal OUT at an output terminal of an operational amplifier Amp has the voltage level of the offset signal OFFSET. Next, when the reset signal Reset is disabled, the analog reference voltage generator starts to operate in response to the first and second clock signals Clk1 and Clk2.
More specifically, as is shown in FIG. 3B, a voltage of the input dump capacitor C1 is discharged and initialized to 0 V during a logic high (or a high level) period of the first clock signal Clk1. As is shown in FIG. 3C, an input voltage, that is, the gain signal CAIN is applied to the input dump capacitor C1 and charges stored at the input dump capacitor C1 are accumulated at the feedback capacitor C2 during a logic high period of the second clock signal Clk2, so that the output signal OUT at the output terminal of the operational amplifier Amp is changed. At this time, the output signal OUT increases as the clock signal Clk1 or Clk2 increases.
As described above, the output signal OUT of the conventional analog reference voltage generator does not increase during the logic high period of the first clock signal Clk1 and increases only during the logic high period of the second clock signal Clk2. Accordingly, a single slope ADC including this conventional analog reference voltage generator needs time corresponding to the period of 1024 pulses of the first or second clock signal Clk1 and Clk2 in order to output 10 bits of data. In addition, when the number of circuits operated by the conventional analog reference voltage generator increases, loading increases, which increases a resistive capacitive (RC) delay. A desired output signal cannot be obtained during the RC delay.